1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a super-junction structure, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, a request for thinning and weight saving for electronic apparatuses has been strong as represented by a liquid crystal television set, a plasma television set, an organic EL (Electro-Luminescence) television set, and the like. Along with the above request, a request for miniaturization and promotion of high performance for power source apparatuses has also been strong. In response to this request, in a power semiconductor element, performance improvements such as high withstand voltage promotion, large current promotion, low loss promotion, high speed promotion and high breaking withstand voltage promotion have attracted attention. For example, a vertical power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) is known as a switching element for a power electronics application.
Each of an ON resistance and a withstand voltage of a MOSFET largely depends on an impurity concentration of an N-type region as a conductive layer of the MOSFET. Although the impurity concentration of the conductive layer is increased for the purpose of reducing the ON resistance, in order to ensure a desired withstand voltage, it is difficult to increase the impurity concentration to some value or more. That is to say, a semiconductor region of a MOSFET through which a source region and a drain region are connected to each other is generally called a drift region (drift layer). In a phase of an ON state of the MOSFET, the drift region becomes a current path, while in a phase of an OFF state of the MOSFET, a withstand voltage of the MOSFET is held based on a depletion layer extending from a pn junction formed by the drift region and a base region.
The ON resistance of the MOSFET depends on an electrical resistance of a conductive layer (drift region). For realization of the low ON resistance, it is expected that an impurity concentration of the drift region is increased to reduce the electrical resistance of the drift region. However, increasing the impurity concentration of the drift region results in that the extension of the depletion layer becomes insufficient, and thus the withstand voltage is reduced. That is to say, although increasing the impurity concentration of the drift region allows the ON resistance to be reduced, there is a limit to increasing the impurity concentration for the purpose of ensuring the desired withstand voltage. As has been described, in the MOSFET, the promotion of the low ON resistance, and the promotion of the high withstand voltage show a trade-off relationship. Thus, improving the trade-off relationship is required for the low power consumption element.
A technique referred to as a MULTI-RESURF structure or a super-junction structure (hereinafter typically referred to as “a super-junction structure”) is known as one technique for breaking through the trade-off. This technique, for example, is described in Japanese Patent Laid-Open Nos. 2004-146689, 2006-313892 and 2007-149736, and Japanese Patent Nos. 3940518 and 3943732 (hereinafter referred to as Patent Documents 1 to 5, respectively).
As described in Patent Documents 1 to 5, a MOSFET including a drift region having a super-junction structure has a structure in which p-type pillar-like semiconductor regions (a P-type region, a p-type pillar region, and a p-type vertical resurf layer), and n-type pillar-like semiconductor regions (an N-type region, an n-type pillar region, and an n-type vertical resurf layer) are disposed periodically, alternately, or in island-like shapes in a direction parallel with a surface of a semiconductor substrate. In other words, the MOSFET concerned has a vertical resurf structure in which the p-type pillar region and the n-type pillar region are alternately, transversely and repetitively disposed within the semiconductor layers disposed so as to hold a source electrode and a drain electrode between the semiconductor layers.
The withstand voltage is held based on a depletion layer extending from a pn junction formed by these semiconductor regions. Even when the extension of the depletion layer becomes small by increasing an impurity concentration for the low ON resistance, each of the widths of these semiconductor regions is made small, which results in that the complete depletion of these semiconductor regions becomes possible. In an ON state, a current is caused to flow through the N-type region of the conductive layer, while in an OFF state, each of the P-type region and the N-type region is completely depleted, thereby making it possible to ensure the withstand voltage. As a result, the promotion of the low ON resistance, and the promotion of the high withstand voltage in the MOSFET can be simultaneously attained.
As has been described, the super-junction structure depends on the width of each of the p-type semiconductor regions, and the width of each of the n-type semiconductor regions between each two p-type semiconductor regions. When each of the widths of the p-type semiconductor region and the n-type semiconductor region is further narrowed, the impurity concentration of the n-type semiconductor region can be further increased. As a result, it is possible to attain the further reduction of the ON resistance, and the promotion of the higher withstand voltage. As can be seen from this, the impurity concentration becomes the point based on which the withstand voltage and the ON resistance are determined.
Therefore, with regard to the preferred form, for the purpose of further increasing the withstand voltage, it becomes important to strike the balance between the impurity of the p-type semiconductor region, and the impurity of the n-type semiconductor region, that is, the so-called charge balance. That is to say, an amount of impurity contained in the p-type semiconductor region, and an amount of impurity contained in the n-type semiconductor region are equalized to each other, whereby the impurity concentration becomes equivalently zero, thereby making it possible to obtain the high withstand voltage. In a phase of reverse bias (in a phase of the OFF state), the complete depletion is realized to hold the high withstand voltage, whereas in a phase of zero bias (in a phase of the ON state), a current is caused to flow through the n-type semiconductor region heavily doped with an n-type impurity, thereby realizing an element having a low ON resistance beyond the material limit.
The low ON resistance element having the super-junction structure greatly contributes to the promotion of the low power consumption in the circuit. However, for the design of the ON resistance, it becomes important to strike the right balance among a resistance of the super-junction structure portion, the ON resistance of the switching transistor, other parasitic resistances, and the like. In the case of a combination with a planar type MOSFET having a channel in a silicon surface, it is necessary to narrow a transverse period of the super-junction structure for the purpose of improving the trade-off between the withstand voltage and the ON resistance by using the super-junction structure. In addition, it is necessary to narrow a transverse period (cell pitch) as well of the MOS gate structure for the purpose of reducing the ON resistance of the entire element.
For this reason, in recent years, a vertical MOSFET having a MOS gate structure as a trench gate structure has been used on a middle or low withstand voltage application instead of using the combination with the planar type MOSFET. The vertical MOSFET has a structure in which a gate insulating film is formed on an inner wall of a relatively shallow trench formed in a base region, and a gate electrode is formed so as to be filled in the trench. In the case of the vertical MOSFET, the high integration can be made for the transistor pitches, which results in that a large effective gate width can be obtained in the same semiconductor area. Thus, the vertical MOSFET is suited to the low ON resistance.
On the other hand, the following three techniques are expected as a method of manufacturing the super-junction structure.
(1) An n-type impurity and a p-type impurity are separately introduced into an epitaxial layer (made of epitaxial silicon) by utilizing an ion implantation method, and the epitaxial structure is repetitively formed multiple times so that the epitaxial structures are laminated in order, thereby manufacturing the super-junction structure (referred to as “a first manufacturing method”). That is to say, the first manufacturing method is a multi-epitaxial manufacturing method in which the same epitaxial growth is repetitively carried out multiple times.
(2) A trench is formed in a thick epitaxial layer, an impurity is introduced into the side surface of the trench by utilizing a diffusion method or the like, and an insulating material or a non-conductive material is filled in the trench (referred to as “a second manufacturing method”).
(3) A trench is formed in a thick epitaxial layer, and silicon containing therein an impurity is filled in the trench in an epitaxial growth process (referred to as “a third manufacturing method”). That is to say, the third manufacturing method is a manufacturing method in which the trench formed once is back-filled with silicon containing therein the impurity in the epitaxial growth process (trench forming epitaxial back-filling manufacturing method).
Moreover, when the vertical MOSFET is adopted as a switching transistor combined with the super-junction structure, how the manufacturing method of the super-junction structures shown in items (1) to (3), and the formation of the relative shallow trench are combined with each other becomes important.
For example, the super-junction structure has become effective in the promotion of the low ON resistance and the chip shrink. However, the optimal sizes exist in an arrangement pitch P1 of pn junctions composing the super-junction structure, and a gate pitch P2 of switching transistors, respectively. Thus, it cannot be said that fulfilling both the arrangement pitch P1 and the gate pitch P2 is usually possible.
The arrangement pitch P1 of the pn junctions is constrained by the deep trench formation and the impurity diffusion. Also, whether the transistor is of the planar type or of the vertical type, the shallow trench technique, the optimization of the gate-to-drain capacitor Qgd, the manufacture process line generation, and the like exert an influence on the gate pitch P2.
For example, there is proposed a case example in which the gate pitch of the vertical transistor is set together with the pitch of the super-junction structure as in the case of the structure described in Patent Document 2, or a case example in which the gate pitch of the vertical transistor is doubled as in the case of the structure described in Patent Document 3.
In addition, there is also proposed a case example in which the arrangement directions of the super-junction structure and the vertical transistor structure are made to perpendicularly intersect with each other, thereby dissolving the restriction condition of the mutual pitches as in the case of the structures described in Patent Documents 4 and 5.